BF2S Forums Is this any good? (Thinking of getting new PC)

Jepeto87 wrote:

Now I cant find my order status on there site, I think its been cancelled! You'd swear they dont want my money!
Ill have to give them a call.

Mail order FTW! (NOT).

I found out today that that happened to me also - I order some vinyl for a friend from HMV - not only have they not sent him the vinyl they've even gone as far as deleting my account on their system!

ph4s3 wrote:

Scorpion0x17 wrote:

ph4s3 wrote:

I don't believe that is correct.  The BIOS maps address space to devices and doesn't use the system RAM that is displaced.  in a 4GB address space, if all 4GB are installed, whatever is mapped to the devices is effectively unmapped from the system RAM so those particular locations will never be accessible.

If you have 3GB of system RAM installed and a 700MB memory footprint, then all 3GB of physical system RAM are addressable and usable, the 700MB of device-mapped memory is addressable, and there's still 300MB or so of address space left available.  However, if you have 4GB of physical system RAM installed and the same 700MB footprint, the 700MB device-mapped memory is addressable and only 3.3GB of physical RAM is addressable, the other 700MB of space on the system RAM doesn't have an address and can't be used. 

The BIOS effectively uses that address space, but it is not using the physical system RAM when it maps memory pointers to installed devices.

WHAT?!

I'm sorry but you clearly don't know enough about what you're talking about.

B.I.O.S. Stands for Basic Input Output System. It is the BIOS that handles ALL the IO - this is done using space within physical memory addresses, and it is all co-ordinated by the BIOS.

Look, I have a BTEC in Computer Studies, A-Level Computer Studies and a BEng(Hons) degree in Software Engineering for Real-Time Systems. I'm not saying this to say "I'm better than you" - I'm saying it because whilst gaining these qualifications I learnt all about how IO and memory mapping works at the hardware level and I, therefore, do know exactly what I'm talking about.

That's nice.  While we're comparing penis size credentials here, I've got a BSEE, have passed my first Professional Engineer license exam and I have developed the hardware and firmware for several embedded systems using MMIO.  Granted, they were 16bit and not x86 architecture, but the principles of MMIO are still the same. 

If you've got a certain size address space and your physical memory is the same size, when you use MMIO you lose access to the memory stack for whatever quantity of addresses you map to the I/O registers because those addresses no longer point at the stack.  The way you put it makes it sound as if some part of that physical RAM is used by the BIOS when it isn't.  It's wasted because the addresses that could use it are reserved and pointing somewhere else and if data were loaded to those addresses it would go to the I/O bus to whatever device has that address assigned to it. 

Perhaps I got the verbiage wrong in regards to the function of the BIOS doing a particular task, but MMIO doesn't get any simpler than that.  You lose whatever you map elsewhere because one address can't go to two different locations. 

And that means you can't get access to 4GB of system RAM on modern computers (x86 types with a 32bit OS), because a portion of that 4GB address space is remapped to the devices in the PC such as the video card.

First up - appologies for not replying sooner - been reading up...

Secondly - as I stated, my quoting my qualifications was not me saying "I'm better than you" - as leetkyle says in the 'Technical Team' thread - there is a preponderance of bad advice in the tech section and so I was just making it clear that I do have some qualifications behind my statements, I'm not just spouting half-learned 'facts' out my arse.

Now, on the matter in hand...

The reason I've been reading up is that reading your description of memory mapped IO, I started to doubt myself - and so I double checked, and well we're both right...

OK, back in the day, cpus talked to the mem and IO devices pretty much like this:

^{(NOTE: the following diagrams are 'simplified' for brevity and clarity - but please remember they are just simplified representative diagrams not in depth detailed diagrams)}



Where the CPU talked to the RAM and IO devices through the RAM and IO data-buses via a seperate memory controller (MC) and IO controller (IOC), respectively.

The problem with that was that the IO data-bus is slow, so as RAM and CPUs got faster this became a bottle-neck.

So, a memory-mapping controller (MMC) was insert between the memory controller and the IO controller, thus:



Each memory mapped device is given a physical memory location and the memory-mapping controller coordinates the synchronisation of the device registers (via the IOC) and their memory spaces (via the MC).

Now, the scheme you described, and this is why I did some reading around, did ring a bell, it would appear is also refered to as 'memory mapping', and is something like (again, this is just representive, not detailed), this:



Where, essentially the MC, MMC and IOC are all combined into one controller that manages both the memory data-bus and the IO data bus, as-well-as the memory mapping. Now, in this architecture, as you correctly state, the IO device register are not actually mapped directly to physical memory locations, rather the combined controller routes the address reference in the appropriate direction.

So, basically, we're both kind of right - we're just describing two different 'memory-mapping' solutions.

And, I will admit, from what I've read, modern CPUs with nice fast IO buses do use 'your' scheme in preference to 'mine' - so I was mistaken in that regard.

You never stop learning.

Last edited by Scorpion0x17 (2007-07-13 16:52:05)

Manicalwizard wrote:

Off topic, how much does everyone think the prices will go down after july 22?

Nowhere near enough for my liking.